1. Field of Invention
The present invention relates to a method of manufacturing an integrated circuit. More particularly, the present invention relates to a semiconductor device and manufacturing method thereof.
2. Description of Related Art
In deep sub-micron integrated circuit manufacturing, the level of device integration has increased considerably. As the level of integration continues to increase, many features including contact area, junction depth and line width must be reduced correspondingly. To boost the performance capacity of such miniature devices, resistance must be reduced and resistance-capacitance (RC) delay in transmitted signals through a conductive wire must be lowered as much as possible. Therefore, a refractory metal silicide layer is often formed on the polysilicon layer of gate in the fabrication of the semiconductor devices. The composite layer comprising the polysilicon layer and the refractory metal silicide layer is referred to as a polycide gate. Among various types of refractory metal silicide compounds, tungsten silicide (WSix) is the most widely used one. The gate structure formed by joining a polysilicon layer and a tungsten silicide layer together is hence called a tungsten polycide gate. The following is a brief description of the conventional method of manufacturing a tungsten polycide gate.
FIGS. 1A through 1D are schematic cross-sectional views showing the steps in a conventional method of fabricating a tungsten polycide gate. First, as shown in FIG. 1A, a substrate 100 is provided. Thereafter, a gate dielectric layer 102 is formed over the substrate 100 and then a doped polysilicon layer 104 is formed over the gate dielectric layer 102.
As shown in FIG. 1B, a tungsten-rich tungsten silicide (WSi, x<2.3) layer 106 is formed over the polysilicon layer 104. Thereafter, a cap layer 108, preferably a silicon nitride layer, is formed over the tungsten-rich tungsten silicide layer 106. A patterned photoresist layer 110 is formed over the cap layer 108.
As shown in FIG. 1C, using the patterned photoresist layer 110 as a mask, the cap layer 108, the tungsten silicide layer 106, the polysilicon layer 104 and the gate oxide layer 102 are sequentially etched to form a stack gate structure 112.
As shown in FIG. 1D, after the patterned photoresist layer 110 is removed, a thermal oxidation process is performed to form silicon oxide liners 114 on the sidewalls of the stack gate structure 112 and on the substrate 100. Thereafter, a silicon nitride protective wall layer 116 is formed on each side of the stack gate structure 112.
In the aforementioned method of fabricating the tungsten polycide gate, the tungsten silicide layer 106 will be exposed immediately after the formation of the stack gate structure 112. Hence, in the thermal oxidation step, the tungsten silicide in the tungsten silicide layer 106 will react with oxygen to form tungsten oxide. Furthermore, in a high-temperature processing environment during a thermal annealing or thermal oxidation operation, lateral extrusions (as shown in FIG. 1D) are often formed on the sides of the tungsten silicide layer 106 due to a phase transition. As line width of semiconductor devices continues to shrink, these lateral extrusions may be so close together that short-circuit between the gate and the conductive section of a subsequently formed contact seems inevitable. When this happens, performance of the device will be immensely affected.
One method of eliminating the lateral extrusions is to increase the silicon content of the tungsten silicide layer. In other words, a silicon-rich (WSix, x>2.3) tungsten silicide layer is formed in the fabrication process. However, increasing the silicon content in the tungsten silicide layer will increase gate resistance. To maintain a constant gate resistance, thickness of the tungsten silicide layer must be increased. Yet, increasing the thickness of the tungsten silicide layer will increase the aspect ratio of the gate leading to greater difficulties in performing a subsequent gate etching and self-aligned contact (SAC) etching process.